This invention relates to the molding and application of protective caps to microelectronic semiconductor chips on a wafer scale as opposed to application on an individual chip basis. More particularly the invention relates to the molding and application of protective caps to semiconductor chips incorporating Micro Electro Mechanical Systems (MEMS). However the invention is not limited to MEMS applications.
Semiconductor chips are normally packaged in a protective layer or layers to protect the chip and its wire bonds from atmospheric and mechanical damage. Existing packaging systems typically use epoxy molding and thermal curing to create a solid protective layer around the chip. This is normally carried out on individually diced chips bonded to lead frames and so must be done many times for each wafer. Alternative methods of packaging include hermetically sealed metal or ceramic packages, and array packages such as ball grid array (BGA) and pin grid array (PGA) packages. Recently wafer scale packaging (WSP) has started to be used. This is carried out at the wafer stage before the chips are separated. The use of molding and curing techniques subjects the wafer to both mechanical and thermal stresses. In addition the protective cap so formed is a solid piece of material and so cannot be used for MEMS devices, since the MEMS device would be rendered inoperable by the polymer material. Existing packaging systems for MEMS devices include thematically sealed packages for individual devices, or use silicon or glass wafer scale packaging, both of which are relatively high cost operation.
In one broad form the invention provides an micro machined accelerometer package including:
a chip having a top surface and a bottom surface and having a micro machined accelerometer formed in the chip, the accelerometer including a mass cantilevered from the remainder of the chip to be movable out of the plane of the chip;
a first hollow molded cap bonded to the top surface over at least part of the accelerometer to define a first cavity into which the cantilevered mass may move,
wherein the first molded cap has been bonded to the chip at the wafer stage prior to separation of the wafer into individual chips.
An array of first caps is preferably bonded simultaneously to the wafer. Preferably the array of first caps is held in alignment with the wafer as the caps are bonded to the wafer with a tool formed of silicon or silicon alloy.
The package may further include a second cap bonded to the bottom surface of the chip to provide a second cavity into which the cantilevered mass may move.